As more and more functional blocks are added, for example, to a chip, an integrated circuit (IC), or an integrated system or device, the risk of generation and propagation of noise between different functional blocks, or within a functional block, may become quite substantial.
An exemplary conventional complementary metal oxide semiconductor (CMOS) transistor arrangement is illustrated in FIG. 1. As shown in FIG. 1, the conventional CMOS transistor arrangement 10 includes an n-channel MOS (NMOS) transistor 30 and a p-channel MOS (PMOS) transistor 40. The conventional CMOS arrangement 10 also includes a p-substrate 20 (e.g., a p−-substrate). The NMOS transistor 30 is disposed in the p-substrate 20. The NMOS transistor 30 includes a p+-body (B), an n+-source (S) and an n+-drain (D) disposed in the p-substrate 20. A voltage source VSS 7 having a ground is coupled to the p+-body (B) and the n+-source (S) of NMOS transistor 30. An input line 5 is coupled to a gate (G) of the NMOS transistor 30. An output line 15 is coupled to the n+-drain (D) of the NMOS transistor 30. The PMOS transistor 40 includes an n-well 50 that is disposed in the p-substrate 20. The PMOS transistor 40 also includes an n+-body (B), a p+-source (S) and a p+-drain (D) disposed in the n-well 50. A voltage source VDD 17 is coupled to the p+-source (S) and the n+-body (B) of PMOS transistor 50. The input line 5 is also coupled to a gate of the PMOS transistor 40. The output line 15 is also coupled to the p+-drain (D) of the PMOS transistor 40.
During normal operation of the conventional CMOS transistor arrangement 10, voltage sources VSS 7 and VDD 17 may be noisy. For example, noise may be caused by other circuitry found on or coupled to the chip that may directly or indirectly affect the voltage sources VSS 7 and VDD 17. High swing or high power devices, such as data drivers in a wire line communication system or transmitters in wireless communications systems, may be sources of noise. Noise may also be caused, for example, by the driving of active circuits. In one example, the voltage sources may be coupled to active circuitry (e.g., active portions of an inverter circuit) which may cause transient currents to flow during signal transitions from a high level to a low level or from a low level to a high level. In another example, noise may be caused by transitions in a signal propagated or generated by the chip.
In the NMOS transistor 30, if the voltage source VSS 7 is noisy, then the noise may propagate to the p-substrate 20 via, for example, at least through the resistive coupling 9 between the p+-body (B) and the p-substrate 20. In the PMOS transistor 40, if the voltage source VDD 17 is noisy, then the noise may propagate to the n-well 50 via the n+-body (B) of the PMOS transistor 40 via a resistive coupling 19. The noise in the n-well 50 may propagate to the p-substrate 20 via, for example, at least the capacitive coupling 29 between the n-well 50 and the p-substrate 20. If the noise is able to propagate to the p-substrate 20, then noise may propagate to or otherwise affect other circuits on or off the chip that may be coupled to the p-substrate 20.
FIG. 1A shows another conventional CMOS arrangement 10, which is similar to the conventional CMOS arrangement 10 shown in FIG. 1, except that a quieter voltage source VSS 3 may be coupled to the p+-body (B) of the NMOS transistor 30 and a noisy voltage source VSS 7 may be coupled to the n+-source (S) of the NMOS transistor 30. Thus, less noise is resistively coupled from the p+-body (B) to the p-substrate 20. To a lesser extent, noise may be capacitively coupled between the n+-source and the p-substrate 20. Noise may be coupled from the PMOS transistor 40 to the p-substrate 20, as described above with respect to the conventional CMOS arrangement 10, and as shown in FIG. 1. In the CMOS arrangement of FIG. 1A, noise may substantially propagate to the p-substrate 20. Accordingly, there is a need to mitigate noise in the substrate of a chip.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.